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Xilinx SDAccel/SDSoC 2018.2 Win/Linux x64 2018
SDAccel™ 開發環境可將數據中心應用加速性能功耗比提高達 25 倍。

SDAccel 是 SDx™ 系列產品之一,提供一個編譯器、一個調試器和一個分析器,  不僅支持標準 OpenCL API,可抽象硬件平台,而且還可優化針對硬件的代碼,就像在 FPGA 加速電路板上運行的內核一樣。

SDSoC™ 開發環境可為異構 Zynq® SoC 及 MPSoC 部署提供類似嵌入式 C/C++/OpenCL 應用的開發體驗,其中包括簡單易用的 Eclipse IDE 和綜合設計環境。SDSoC 提供業界首款 C/C++/OpenCL 全系統優化編譯器,可實現系統級的特性描述、可編程邏輯中的自動軟件加速、自動系統連接生成以及可加速編程的各種庫。此外,它還可幫助最終用戶及第三方平台開發人員快速定義、集成和驗證系統級解決方案,為其最終用戶實現定製化編程環境。

Xilinx OpenCV 庫現已推出,包含 50 多項硬件優化 OpenCV 功能,包括 Gausian、 Median、Bilateral、Harris corner、 Canny edge detection、HoG、ORB、SVM、LK Optical Flow 及更多
簡單易用的 Eclipse IDE 可用於開發支持嵌入式 C/C++/OpenCL 應用的完整 Zynq SoC 和 MPSoC
只需一點按鈕,就可對可編程邏輯 (PL) 中的功能進行加速
支持作為目標 OS 的裸機、Linux 與 FreeRTOS
系統級的特性描述

快速性能估算與面積估算可在幾分鐘內完成,包括 PS、數據通信以及 PL
高速緩存、存儲器以及總線利用率的自動運行時儀表
可實現最佳總體系統架構的便捷生成與探索
sdsoc-uopdate
全系統優化編譯器

可將 C/C++/OpenCL 應用編譯成全功能 Zynq SoC 與 MPSoC 系統
可在生成 ARM 軟件與 FPGA 比特流的可編程邏輯中實現自動功能加速
不僅可優化系統連接,而且還支持吞吐量、時延以及面積權衡的快速系統探索
面向平台開發人員的專家級使用模型

通過業經驗證方法實現的目標定製電路板可將現有的 Vivado 項目及軟件項目轉換成 SDSoC
面向 Zynq 開發板的開發板支持包 (BSP) 現已開始提供,包括 ZC702、ZC706 以及第三方開發板和系統級模塊 (SoM)(包括 Zedboard、Microzed、Zybo、Avnet 嵌入式視覺套件、視頻和成像套件以及 SDR 套件等)。請單擊“開發板與模塊”查看全面的 BSP 列表。
x64 | Language:English 
Description:
SDAccel is an OpenCL programming system, C / C ++ for heterogeneous systems with the implementation of hardware accelerators on Xilinx FPGA. OpenCL is one of the applications of the C ++ language for the development of FPGA firmware. SDAccel supports any combination of OpenCL, C, and C ++ cores with libraries for FPGA design. This environment allows parallel programming of both the central processor and FPGA accelerators.
SDSoC development environment is intended only for Zynq (this is a chip in which there is a FPGA and an AWP processor in one package).
Add. Information : Starting with version 2016.3, SDAccel and SDSoC combined into one package called SDx. SDSoC works in Windows and Linux. SDAccel only works under some versions of Linux.
SDSoC and SDAccel are characterized by the fact that the FPGA project already fades into the background. In the foreground - the algorithm. Both systems allow modeling at the level of the original algorithm written in C / C ++ and then translate it to FPGA. This allows you to dramatically increase the complexity of the algorithm.
If we compare the programming for the FPGA on VHDL / Verilog and on C / C ++, then it begs the analogy between programming for conventional processors in C / C ++ and assembler. In an assembler, you can make a more compact and fast code, and in C / C ++ you can write a more complex program.

Details:
Xilinx SDAccel/SDSoC 2018.2
Year/Date of Release:2018
Version:2018.2
Developer:Xilinx Inc.
Architecture:64bit
Language:English
Medicine:Present

System Requirements:

System requirements SDAccel:
The presence of one of the accelerators:
-the Xilinx Kintex UltraScale KCU1500 the FPGA Reconfigurable Acceleration card based on XCKU115-FLVB2104-2 the FPGA-E,
-the Xilinx the Virtex UltraScale + VCU1525 the FPGA Reconfigurable Acceleration card based on XCVU9P-L2FSGD2104E FPGA.
-Host computer for an accelerator with the characteristics Mat.
-card with support for PCIe Gen3 X8 slot,64GB OP,
-Disk:100 GB of free hard disk space.

Computer for programming:
PC with installed environment Vivado Design Suite 2018.2 and Xilinx Platform Cable USB 2 (HW-USB-II-G).
OS Red Hat Enterprise Workstation / Server 7.3-7.4 (64-bit), CentOS 7.2, Ubuntu Linux 16.04.3 LTS (64-bit)

SDSoC system requirements:
One of the following developer platforms:
-ZC702, ZC706, ZedBoard based on Zynq- 7000 SoC,
-ZCU102, ZCU104, ZCU106 based on Zynq UltraScale + MPSoC.
For Windows version: Microsoft Windows 7 / 8.x / 10 Professional (64-bit)
For Linux version: Red Hat Enterprise Workstation OS 6.7 / 6.8, Red Hat Enterprise Workstation Server / Server 7.3-7.4 (64-bit), CentOS 7.2 / 7.3 / 7.4 (64-bit), Ubuntu Linux 16.04.3 LTS (64-bit )

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